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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003, zarlink semiconductor inc. all rights reserved. features ? supports at&t tr62411 and bellcore gr- 1244-core stratum 4 enhanced and stratum 4 timing for ds1 interfaces ? supports etsi ets 300 011, tbr 4, tbr 12 and tbr 13 timing for e1 interfaces ? selectable 1.544mhz, 2.048mhz or 8khz input reference signals ? provides c1.5, c2, c3 , c4 , c8 and c16 output clock signals ? provides 3 different styles of 8 khz framing pulses ? attenuates wander from 1.9 hz applications ? synchronization and timing control for multitrunk t1 and e1 systems ? st-bus clock and frame pulse sources description the MT9041b t1/e1 system synchronizer contains a digital phase-locked loop (dpll), which provides timing and synchronization signals for multitrunk t1 and e1 primary rate transmission links. the MT9041b generates st-bus clock and framing signals that are phase locked to either a 2.048mhz, 1.544mhz, or 8khz input reference. the MT9041b is compliant with at&t tr62411 and bellcore gr-1244-core stratum 4 enhanced, stratum 4, and etsi ets 300 011. it will meet the jitter tolerance, jitter transfer , intrinsic jitter, frequency accuracy, capture range and phase change slope requirements for these specifications. november 2003 ordering information MT9041bp 28 pin plcc -40 c to +85 c MT9041b t1/e1 system synchronizer data sheet figure 1 - functional block diagram zarlink semiconductor us patent no. 5,602,884, uk patent no. 0772912, france brevete s.g.d.g. 0772912; germany dbp no. 69502724.7-08 mode select divider output interface circuit ms fs1 fs2 rst vdd vss c3o c1.5o c2o c4o c8o c16o f0o f8o f16o ref osci osco phase detector filter dco loop
MT9041b data sheet 2 zarlink semiconductor inc. figure 2 - pin connections pin description pin # name description 1v ss ground. 0 volts. 2ic0 internal connect. connect to vss 3nc no connect. connect to vss 4ref reference (ttl input). pll reference clock. 5v dd positive supply voltage. +5v dc nominal. 6osco oscillator master cloc k (cmos output). for crystal operation, a 20mhz crystal is connected from this pin to osci, see figure 6. for clock oscillator operation, this pin is left unconnected, see figure 5. 7osci oscillator master clock (cmos input). for crystal operation, a 20mhz crystal is connected from this pin to osco, see figure 6. for clock oscillator operation, this pin is connected to a clock source, see figure 5. 8f16o frame pulse st-bus 16.3 84mb/s (cmos output). this is an 8khz 61ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st-bus operation at 16.384mb/s. see figure 11. 9f0o frame pulse st-bus 2. 048mb/s (cmos output). this is an 8khz 244ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st-bus operation at 2.048mb/s and 4.096mb/s. see figure 11. 10 f8o frame pulse st-bus 8.192mb/s (cmos output). this is an 8khz 122ns active high framing pulse, which marks the beginning of an st-bus frame. this is used for st-bus operation at 8.192mb/s. see figure 11. 11 c1.5o clock 1.544mhz (cmos output). this output is used in t1 applications. 12 c3o clock 3.088mhz (cmos output). this optional output is used in t1 applications. 13 c2o clock 2.048mhz (cmos output). this output is used for st-bus operation at 2.048mb/s. 14 c4o clock 4.096mhz (cmos output). this output is used for st-bus operation at 2.048mb/s and 4.096mb/s. 1 6 5 432 7 8 9 10 11 23 19 20 21 22 24 25 26 27 28 vss ic0 nc ref vdd osco osci f16o f0o f8o c1.5o ic0 ic1 ic0 ic0 ms ic0 ic0 fs2 fs1 rst 12 13 14 15 16 17 18 c2o vss c8o c16 o vdd c4o c3o MT9041b
MT9041b data sheet 3 zarlink semiconductor inc. functional description the MT9041b is a system synchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for t1 and e1 primary rate digital transmission links. figure 1 is a functional block diagram which is described in the following sections. frequency select mux circuit the MT9041b operates on the falling edges of one of three possible input reference frequencies (8khz, 1.544mhz or 2.048mhz). the frequency select inputs (fs1 and fs2) determine which of the three frequencies may be used at the reference input (ref). a reset (rst ) must be performed after every freque ncy select input change. operation with fs1 and fs2 both at logic low is reserved and must not be used. see table 1. table 1 - input frequency selection 15 v ss ground. 0 volts. 16 c8o clock 8.192mhz (cmos output). this output is used for st-bus operation at 8.192mb/s. 17 c16o clock 16.384mhz (cmos output). this output is used for st -bus operation at 16.384mb/s. 18 v dd positive supply voltage. +5v dc nominal. 19 ic0 internal connect. connect to vss 20 ic1 internal connect. leave open circuit 21 ic0 internal connect. connect to vss 22 ic0 internal connect. connect to vss 23 ms mode/control select (ttl input). this pin, determines the device?s state (normal, or freerun) of operation. the logic level at this input is gated in by the rising edge of f8o. see table 3. 24 ic0 internal connect. connect to vss 25 ic0 internal connect. connect to vss 26 fs2 frequency select 2 (ttl input). this input, in conjunction with fs1, selects which of three possible frequencies (8khz, 1.544mhz, or 2.04 8mhz) may be input to the ref input. see table 1. 27 fs1 frequency select 1 (ttl input). see pin description for fs2. 28 rst reset (schmitt input). a logic low at this input resets the MT9041b. to ensure proper operation, the device must be reset after re ference signal frequency changes and power-up. the rst pin should be held low for a minimum of 300ns. while the rst pin is low, all frame and clock outputs are at logic high. following a reset, the input reference source and output clocks and frame pulses are phase aligned as show n in figure 10. fs2 fs1 input frequency 00 reserved 01 8khz 1 0 1.544mhz 1 1 2.048mhz pin description (continued) pin # name description
MT9041b data sheet 4 zarlink semiconductor inc. digital phase lock loop (dpll) the dpll of the MT9041b consists of a phase detector, li miter, loop filter, digitally controlled oscillator, and a control circuit (see figure 3). phase detector - the phase detector compares the primary refe rence signal (ref) with the feedback signal from the frequency select mux circuit, and provides an error signal corresponding to the phase difference between the two. this error signal is passed to the limiter circuit. the frequency select mux allows the proper feedback signal to be externally selected (e.g., 8khz, 1.544mhz or 2.048mhz). limiter - the limiter receives the error signal from the phas e detector and ensures that the dpll responds to all input transient conditions with a maximum output phase slo pe of 5ns per 125us. this is well within the maximum phase slope of 7.6ns per 125us or 81ns per 1.326m s specified by bellcore gr-1244-core stratum 4e. figure 3 - dpll block diagram loop filter - the loop filter is similar to a first order low pass filter with a 1.9 hz cutoff frequency for all three reference frequency selections (8khz, 1.544mhz or 2.0 48mhz). this filter ensures that the jitter transfer requirements in ets 300 011 and at&t tr62411 are met. control circuit - the control circuit sets the mode of the dpll. the two possible modes are normal and freerun. digitally controlled oscillator (dco) - the dco receives the limited and filt ered signal from the loop filter, and based on its value, generates a corresponding digital output signal. the synchronization method of the dco is dependent on the state of the MT9041b. in normal mode, the dco provides an output signal whic h is frequency and phase locked to the selected input reference signal. in freerun mode, the dco is free running with an a ccuracy equal to the accuracy of the osci 20mhz source. output interface circuit the output of the dco (dpll) is used by the output inte rface circuit to provide the output signals shown in figure 4. the output interface circuit uses two tapped delay lines followed by a t1 divider circuit and an e1 divider circuit to generate the required output signals. two tapped delay lines are used to generate a 16.384mhz and a 12.352mhz signals. the e1 divider circuit uses the 16.384mhz signal to generate four clock outputs and three frame pulse outputs. the c8o, c4o and c2o clocks are generated by simply dividing the c16o clock by two, four and eight respectively. these outputs have a nominal 50% duty cycle. the t1 divider circuit uses the 12.384mhz signal to generate two clock outputs. c1.5o and c3o are generated by dividing the inte rnal c12 clock by four and ei ght respectively. these outputs have a nominal 50% duty cycle. control circuit feedback signal from frequency select mux dpll reference to output interface circuit ref reference limiter loop filter digitally controlled oscillator phase detector
MT9041b data sheet 5 zarlink semiconductor inc. figure 4 - output interface circuit block diagram the frame pulse outputs (f0o , f8o, f16o ) are generated directly from the c16 clock. the t1 and e1 signals are generated from a common dpll signal. consequently, the clock outputs c1.5o, c3o , c2o, c4o , c8o, c16o , f0o and f16o are locked to one another for all operating states, and are also locked to the selected input reference in normal mode. see figures 11 and 12. all frame pulse and clock outputs have limited driving capability, and should be buffered when driving high capacitance (e.g. 30pf) loads. master clock the MT9041b can use either a clock or crystal as the master timing source. for recommended master timing circuits, see the applications - master clock section. control and modes of operation the MT9041b can operate either in normal or freerun modes. as shown in table 2, pin ms selects between normal and freerun modes. ms description of operation 0normal 1 freerun table 2 - operating modes tapped delay line from dpll t1 divider e1 divider 16mhz 12mhz c3o c1.5o c2o c4o c8o c16o f0o f8o f16o tapped delay line
MT9041b data sheet 6 zarlink semiconductor inc. normal mode normal mode is typically used when a slave clock source synchronized to the network is required. in normal mode, the MT9041b provides timing (c1.5o, c2o, c3o , c4o , c8o and c16o ) and frame synchronization (f0o , f8o, f16o ) signals, which are synchronized to reference input (ref). the input reference signal may have a nominal frequency of 8khz, 1.544mhz or 2.048mhz. from a reset condition, the MT9041b will take up to 25 seconds for the output signal to be phase locked to the reference. the reference frequencies are selected by the freque ncy control pins fs2 and fs1 as shown in table 1. freerun mode freerun mode is typically used when a master clock source is required, or immediately following system power-up before network synchronization is achieved. in freerun mode, the MT9041b provides timing and synchronization signals which are based on the master clock frequency (osci) only, and are not synchronized to the reference signal (ref). the accuracy of the output clock is equal to th e accuracy of the master clock (osci). so if a 32ppm output clock is required, the master clock must also be 32ppm. see applications - crystal and clock oscillator sections. MT9041b measures of performance the following are some synchronizer performance indicators and their corresponding definitions. intrinsic jitter intrinsic jitter is the jitter produced by the synchronizing ci rcuit and is measured at it s output. it is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. intrinsic jitter may also be measured when the device is in a non-synchronizi ng mode, i.e. free running mode, by measuring the output jitter of the device. intrinsic jitter is usually measured with various bandlimiting filters depending on the applicable standards. jitter tolerance jitter tolerance is a measure of the ability of a pll to operat e properly (i.e., remain in lo ck and or regain lock), in the presence of large jitter magnitudes at various jitter frequenc ies applied to its reference. the applied jitter magnitude and jitter frequency depends on the applicable standards. jitter transfer jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. input jitter is applied at various amplitudes and freq uencies, and output jitter is measured with various filters depending on the applicable standards. for the MT9041b, two internal elements determine the jitter attenuation. this includes the internal 1.9hz low pass loop filter and the phase slope limiter. the phase slope limiter limits the output phase slope to 5ns/125us. therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i.e., attenuated) to 5ns/125us. the MT9041b has nine outputs with three possible input frequencies for a total of 27 possible jitter transfer functions. however, the data sheet section on ac electr ical characteristics - jitter transfer specifies transfer values for only three cases, 8khz to 8khz, 1.544mhz to 1.544mhz and 2.048mhz to 2.048mhz. since all outputs are derived from the same signal, these transfer values apply to all outputs.
MT9041b data sheet 7 zarlink semiconductor inc. it should be noted that 1ui at 1.544mhz is 644ns, wh ich is not equal to 1ui at 2.048mhz, which is 488ns. consequently, a transfer value using different input and output frequencies must be calculated in common units (e.g. seconds) as shown in the following example. what is the t1 and e1 output jitter when the t1 input jitt er is 20ui (t1 ui units) and the t1 to t1 jitter attenuation is 18db? using the above method, the jitter attenuation can be calcul ated for all combinations of inputs and outputs based on the three jitter transfer functions provided. note that the resulting jitter transfer functions for a ll combinations of inputs (8khz, 1.544mhz, 2.048mhz) and outputs (8khz, 1.544mhz, 2.048mhz, 4. 096mhz, 8.192mhz, 16.384mhz) for a given input signal (jitter frequency and jitter amplitude) are the same. since intrinsic jitter is always present, jitter attenuation wi ll appear to be lower for small input jitter signals than for large ones. consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g. 75% of the specified maximum jitter tolerance). frequency accuracy frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. for the MT9041b, the freerun accuracy is equal to the master clock (osci) accuracy. capture range also referred to as pull-in range. this is the input frequ ency range over which the synchronizer must be able to pull into synchronization. the MT9041b capture range is equal to 230ppm minus the accuracy of the master clock (osci). for example, a 32ppm master clock result s in a capture range of 198ppm. lock range this is the input frequency range over which the synchroni zer must be able to mainta in synchronization. the lock range is equal to the capture range for the MT9041b. phase slope phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. the given signal is typically the out put signal. the ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. outputt 1 inputt 1 a ? 20 ------ ?? ?? 10 = outputt 1 20 18 ? 20 -------- - ?? ?? 10 2.5ui t 1 () == outpute 1 outputt 1 644ns () 488ns () ------------------- 3.3ui t 1 () = = outpute 1 outputt 1 1uit 1 () 1uie 1 () ---------------------- =
MT9041b data sheet 8 zarlink semiconductor inc. phase continuity phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. usually, the given timing signal and the ideal timing signal are of the same frequency. phase continuity applies to the output of the synchronizer af ter a signal disturbance due to a reference switch or a mode change. the observation period is usually the time fr om the disturbance, to just after the synchronizer has settled to a steady state. in the case of the MT9041b, the output signal phase continuity is maintained to within 5ns at the instance (over one frame) of mode changes. the total phase shift may accumulate up to 200ns over many frames. the rate of change of the 200ns phase shift is limited to a maximum phase slope of approximately 5ns/125us. this meets the bellcore gr-1244-core maximum phase slope requirement of 7.6ns/125us (81ns/1.326ms). phase lock time this is the time it takes the synchronizer to phase lock to the input signal. phase lock occurs when the input signal and output signal are not changing in phase with respect to each other (not including jitter). lock time is very difficult to determine because it is affected by many factors which include: i) initial input to output phase difference ii) initial input to output frequency difference iii) synchronizer loop filter iv) synchroni zer limiter although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. for instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. and better (smaller) phase slope performance (limite r) results in longer lock time s. the MT9041b loop filter and limiter were optimized to meet the at&t tr62411 jitter transfer and phase slope requirements. consequently, phase lock time, which is not a standards requirement, may be longer than in other applications. see ac electrical characteristics - performance for maximum phase lock time. MT9041b and network specifications the MT9041b fully meets all applicable pll requirements (intri nsic jitter, jitter toleranc e, jitter transfer, frequency accuracy, capture range and phase change slope) for the following specifications. 1. bellcore gr-1244-core issue 1, june 1995 for stratum 4 enhanced and stratum 4 2. at&t tr62411 (ds1) december 1990 for stratum 4 enhanced and stratum 4 3. ansi t1.101 (ds1) february 1994 for stratum 4 enhanced and stratum 4 4. etsi 300 011 (e1) april 1992 for single access and multi access 5. tbr 4 november 1995 6. tbr 12 december 1993 7. tbr 13 january 1996 8. itu-t i.431 march 1993 applications this section contains MT9041b application specific detai ls for clock and crystal operation, reset operation and power supply decoupling. master clock the MT9041b can use either a clock or crystal as the master timing source.
MT9041b data sheet 9 zarlink semiconductor inc. in freerun mode, the frequency tolerance at the clock outpu ts is identical to the frequency tolerance of the source at the osci pin. for applications not requiring an accu rate freerun mode, tolerance of the master timing source may be 100ppm. for applications requiring an accurate freerun mode, such as bellcore gr-1244-core, the tolerance of the master timing source must be no greater than 32ppm. another consideration in determining the accuracy of the master timing source is the desired capture range. the sum of the accuracy of the master timing source and the capture range of the MT9041b will always equal 230ppm. for example, if the master timing source is 100ppm, then the capture range will be 130ppm. clock oscillator - when selecting a clock oscillator, numerous parameters must be considered. these include absolute frequency, freq uency change over temperature, output rise and fall times, output levels and duty cycle. see ac electrical characteristics. figure 5 - clock oscillator circuit for applications requiring 32ppm clock accuracy, the following clock oscillator module may be used. cts cxo-65-hg-5-c-20.0mhz frequency: 20mhz tolerance: 25ppm 0c to 70c rise & fall time: 8ns (0.5v 4.5v 50pf) duty cycle: 45% to 55% the output clock should be connected directly (not ac coupled) to the osci input of the MT9041b, and the osco output should be left open as shown in figure 5. +5v 20mhz out gnd 0.1uf +5v osco MT9041b osci no connection
MT9041b data sheet 10 zarlink semiconductor inc. crystal oscillator - alternatively, a crystal oscillator may be used. a complete oscillator circuit made up of a crystal, resistor and capaci tors is shown in figure 6. figure 6 - crystal oscillator circuit the accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. typically, for a 20mhz crystal specified with a 32pf load capacitance, each 1pf change in load capacitance contributes approximately 9ppm to the frequency devi ation. consequently, capacitor tolerances, and stray capacitances have a major effect on the accuracy of the oscillator frequency. the trimmer capacitor shown in figure 6 may be used to compensate for capacitive effe cts. if accuracy is not a concern, then the trimmer may be removed, the 39pf capacitor may be increased to 56pf, and a wider tolerance crystal may be substituted. the crystal should be a fundamental mode type - not an overtone. the fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to ge nerate spurious responses. the crystal specification is as follows. frequency: 20mhz tolerance: as required oscillation mode: fundamental resonance mode: parallel load capacitance: 32pf maximum series resistance: 35 ? approximate drive level: 1mw e.g., cts r1027-2bb-20.0mhz ( 20ppm absolute, 6ppm 0c to 50c, 32pf, 25 ? ) osco 56pf 1m ? 39pf 3-50pf 20mhz MT9041b osci 100 ? 1uh 1uh inductor: may improve stability and is optional
MT9041b data sheet 11 zarlink semiconductor inc. reset circuit a simple power up reset circuit with about a 50us reset low time is shown in figure 7. resistor r p is for protection only and limits current into the rst pin during power down conditions. the reset low time is not critical but should be greater than 300ns. figure 7 - power-up reset circuit power supply decoupling the MT9041b has two vdd (+5v) pins and two vss (gnd) pins. power and decoupling capacitors should be included as shown in figure 8. figure 8 - power supply decoupling +5v rst r p 1k ? c 10nf r 10k ? MT9041b c2 0.1uf MT9041b + 18 5 1 15 + c1 0.1uf
MT9041b data sheet 12 zarlink semiconductor inc. figure 9 - multiple e1 reference sources with MT9041b multiple e1 re ference sources with MT9041b in this example 8 e1 link framer s (mt9074) are connecte d to a common system ba ckplane clock using the MT9041b. each of th e extracted clocks e1.5o go to a mux which se lects one of the eight input clocks as the reference to the MT9041b. the clock choice is made by a controller using the loss of signal pin los from the mt9074s to qualify potential references. in the event of loss of signal by one of the fram ers, an interrupt signals the controller to choose a different refe rence clock. disturbanc es in the generated syst em backplane clocks c4b and f0b are minimized by the phase slope limitations of the MT9041b pll. this ensures system integrity and minimizes the effect of clock s witchover on downstream trunks. 1k ? 10nf MT9041b f0o c4o fs1 fs2 osci out rst 10k ? mt9074 f0i c4b ttip tring rtip rring los e1.5o 20mhz 32ppm clock + 5v + 5v link 0 mt9074 f0i c4b ttip tring rtip rring los e1.5o links 1-7 ms ref out in0 in1 in2 in3 in4 in5 in6 in7 1 to 8 mux 20mhz to controller interrupt to controller interrupt
MT9041b data sheet 13 zarlink semiconductor inc. * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. * supply voltage and operating temperature are as per recommended operating conditions. absolute maximum ratings* - voltages are with respect to ground (v ss ) unless otherwise stated. parameter symbol min max units 1 supply voltage v dd -0.3 7.0 v 2 voltage on any pin v pin -0.3 v dd +0.3 v 3 current on any pin i pin 20 ma 4 storage temperature t st -55 125 c 5 plcc package power dissipation p pd 900 mw recommended operating conditions - voltages are with respect to ground (vss) unless otherwise stated characteristics sym min typ max units 1 supply voltage v dd 4.5 5.0 5.5 v 2 operating temperature t a -40 25 85 c dc electrical characteristics* - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min max units conditions/notes 1 supply current with:osci = 0v i dds 0.5 ma outputs unloaded 2 osci = clock i dd 60 ma outputs unloaded 3 ttl high-level input voltage v ih 2.0 v 4 ttl low-level input voltage v il 0.8 v 5 cmos high-level input voltage v cih 0.7v dd vosci 6 cmos low-level input voltage v cil 0.3v dd vosci 7 schmitt high-level input voltage v sih 2.3 v rst 8 schmitt low-level input voltage v sil 0.8 v rst 9 schmitt hysteresis voltage v hys 0.4 v rst 10 input leakage current i il -50 +50 av i =v dd or 0v 11 high-level output voltage v oh 2.4v v i oh =10ma 12 low-level output voltage v ol 0.4v v i ol =10ma
MT9041b data sheet 14 zarlink semiconductor inc. ? see "notes" following ac electrical characteristics tables. * supply voltage and operating temperature are as per recommended operating conditions. * timing for input and output signals is based on the worst chislehurst of the combination of ttl and cmos thresholds. * see figure 10. figure 10 - timing parameter measurement voltage levels ac electrical characteristics - performance characteristics sym min max units conditions/notes ? 1 freerun mode accuracy with osci at: 0ppm -0 +0 ppm 2-5 2 32ppm -32 +32 ppm 2-5 3 100ppm -100 +100 ppm 2-5 4 capture range with osci at: 0ppm -230 +230 ppm 1,3-5,37 5 32ppm -198 +198 ppm 1,3-5, 37 6 100ppm -130 +130 ppm 1,3-5,37 7 phase lock time 30 s 1, 3-11 8 output phase continuity with: 9 mode switch to normal 200 ns 1-11 10 mode switch to freerun 200 ns 1, 3-11 11 output phase slope 45 us/s 1-11, 24 ac electrical characteristics - timing parameter measurement voltage levels* - voltages are with respect to ground (vss) unless otherwise stated characteristics sym schmitt ttl cmos units 1 threshold voltage v t 1.5 1.5 0.5v dd v 2 rise and fall threshold voltage high v hm 2.3 2.0 0.7v dd v 3 rise and fall threshold voltage low v lm 0.8 0.8 0.3v dd v t irf, t orf timing reference points all signals v hm v t v lm t irf, t orf
MT9041b data sheet 15 zarlink semiconductor inc. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - input/output timing characteristics sym min max units 1 reference input pulse width high or low t rw 100 ns 2 reference input rise or fall time t irf 10 ns 3 8khz reference input to f8o delay t r8d -21 6 ns 4 1.544mhz reference input to f8o delay t r15d 337 363 ns 5 2.048mhz reference input to f8o delay t r2d 222 238 ns 6f8o to f0o delay t f0d 110 134 ns 7f16o setup to c16o falling t f16s 11 35 ns 8f16o hold from c16o rising t f16h 020ns 9 f8o to c1.5o delay t c15d -51 -37 ns 10 f8o to c3o delay t c3d -51 -37 ns 11 f8o to c2o delay t c2d -13 2 ns 12 f8o to c4o delay t c4d -13 2 ns 13 f8o to c8o delay t c8d -13 2 ns 14 f8o to c16o delay t c16d -13 2 ns 15 c1.5o pulse width high or low t c15w 309 339 ns 16 c3o pulse width high or low t c3w 149 175 ns 17 c2o pulse width high or low t c2w 230 258 ns 18 c4o pulse width high or low t c4w 111 133 ns 19 c8o pulse width high or low t c8w 52 70 ns 20 c16o pulse width high or low t c16wl 24 35 ns 21 f0o pulse width low t f0wl 230 258 ns 22 f8o pulse width high t f8wh 111 133 ns 23 f16o pulse width low t f16wl 52 70 ns 24 output clock and frame pulse rise or fall time t orf 9ns 25 input controls setup time t s 100 ns 26 input controls hold time t h 100 ns
MT9041b data sheet 16 zarlink semiconductor inc. figure 11 - input to output timing (normal mode) figure 12 - output timing 1 t rw t r15d t r2d t r8d f8o notes: 1. input to output delay values are valid after a trst or rst with no further state changes v t v t v t v t ref 8khz ref 2.048mhz ref 1.544mhz t rw t rw t f16wl t f8wh t c15w t c15d t c3d t c4d t c16d t c8d t f16s t f0d f0o f16o c16o c8o c4o c2o c3o c1.5o t c2d f8o t c4w t f0wl t c16wl t c8w t c2w t c3w t c8w t c4w t c3w v t v t v t v t v t v t v t v t v t t f16h
MT9041b data sheet 17 zarlink semiconductor inc. figure 13 - input controls setup and hold timing ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - intrinsic jitter unfiltered characteristics sym min max units conditions/notes? 1 intrinsic jitter at f8o (8 khz) 0.0002 uipp 1-11,18-21,25 2 intrinsic jitter at f0o (8khz) 0.0002 uipp 1-11,18-21,25 3 intrinsic jitter at f16o (8khz) 0.0002 uipp 1-11,18-21,25 4 intrinsic jitter at c1.5o (1 .544mhz) 0.030 uipp 1-11,18-21,26 5 intrinsic jitter at c2o (2 .048mhz) 0.040 uipp 1-11,18-21,27 6 intrinsic jitter at c3o (3.088mhz) 0.060 uipp 1-11,18-21,28 7 intrinsic jitter at c4o (4.096mhz) 0.080 uipp 1-11,18-21,29 8 intrinsic jitter at c8o (8 .192mhz) 0.160 uipp 1-11,18-21,30 9 intrinsic jitter at c16o (16.384mhz) 0.320 uipp 1-11,18-21,33 ac electrical characteristics - c1.5o (1.544mhz) intrinsic jitter filtered characteristics sym min max units conditions/notes? 1 intrinsic jitter (4hz to 100kh z filter) 0.015 uipp 1-11,18-21,26 2 intrinsic jitter (10hz to 40khz filter) 0.010 uipp 1-11,18-21,26 3 intrinsic jitter (8khz to 40khz filter) 0.010 uipp 1-11,18-21,26 4 intrinsic jitter (10hz to 8khz filter) 0.005 uipp 1-11,18-21,26 ac electrical characteristics - c2o (2.048mhz) intrinsic jitter filtered characteristics sym min max units conditions/notes? 1 intrinsic jitter (4hz to 100khz filter) 0.015 uipp 1-11, 18-21, 27 2 intrinsic jitter (10hz to 40khz filter) 0.010 uipp 1-11, 18-21, 27 3 intrinsic jitter (8khz to 40khz filter) 0.010 uipp 1-11, 18-21, 27 4 intrinsic jitter (10hz to 8khz filter) 0.005 uipp 1-11, 18-21, 27 t h t s f8o ms v t v t
MT9041b data sheet 18 zarlink semiconductor inc. ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - 8khz input to 8khz output jitter transfer characteristics sym min max units conditions/notes? 1 jitter attenuation for 1hz@0.01uipp input 0 6 db 1,3,6-11,18-19,21,25,32 2 jitter attenuation for 1hz@0.54uipp input 6 16 db 1,3,6-11,18-19,21,25,32 3 jitter attenuation for 10hz@0.10uipp input 12 22 db 1,3,6-11,18-19,21,25,32 4 jitter attenuation for 60hz@0.10uipp input 28 38 db 1,3,6-11,18-19,21,25,32 5 jitter attenuation for 300hz@0.10uipp input 42 db 1,3,6-11,18-19,21,25,32 6 jitter attenuation for 3600hz@0.005uipp input 45 db 1,3,6-11,18-19,21,25,32 ac electrical characteristics - 1.544mhz input to 1.544mhz output jitter transfer characteristics sym min max units conditions/notes? 1 jitter attenuation for 1hz@20uipp input 0 6 db 1,4,6-11,18-19,21,26,32 2 jitter attenuation for 1hz@104uipp in put 6 16 db 1,4,6-11 ,18-19,21,26,32 3 jitter attenuation for 10hz@20uipp input 12 22 db 1,4,6-11,18-19,21,26,32 4 jitter attenuation for 60hz@20uipp input 28 38 db 1,4,6-11,18-19,21,26,32 5 jitter attenuation for 300hz@20uipp input 42 db 1,4,6-11,18-19,21,26,32 6 jitter attenuation for 10khz@0.3uipp input 45 db 1,4,6-11,18-19,21,26,32 7 jitter attenuation for 100khz@0.3uipp input 45 db 1,4,6-11,18-19,21,26,32
MT9041b data sheet 19 zarlink semiconductor inc. ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - 2.048mhz input to 2.048mhz output jitter transfer characteristics sym min max units conditions/notes? 1 jitter at output for 1hz@3.00uipp input 2.9 uipp 1,5,6-11,18-19,21,27,32 2 with 40hz to 100khz filter 0. 09 uipp 1-5,6-11,18-19, 21,27,33 3 jitter at output for 3hz@2.33uipp input 1.3 uipp 1,5,6-11,18-19,21,27,32 4 with 40hz to 100khz filter 0. 10 uipp 1-5,6-11,18-19,21,2733 5 jitter at output for 5hz@2.07uipp input 0.80 uipp 1,5,6-11,18-19,21,27,32 6 with 40hz to 100khz filter 0. 10 uipp 1-5,6-11,18-19, 21,27,33 7 jitter at output for 10hz@1.76uipp input 0.40 uipp 1,5,6-11,18-19,21,27,32 8 with 40hz to 100khz filter 0. 10 uipp 1-5,6-11,18-19, 21,27,33 9 jitter at output for 100hz@1.50uipp input 0.06 uipp 1,5,6-11,18-19,21,27,32 10 with 40hz to 100khz filter 0. 05 uipp 1-5,6-11,18-19, 21,27,33 11 jitter at output for 2400hz@1.50uipp input 0.04 uipp 1,5,6-11,18-19,21,27,32 12 with 40hz to 100khz filter 0. 03 uipp 1-5,6-11,18-19,21,27,33 13 jitter at output for 100khz@0.20uipp input 0.04 uipp 1,5,6-11,18-19,21,27,32 14 with 40hz to 100khz filter 0. 02 uipp 1-5,6-11,18-19,21,27,33 ac electrical characteristics - 8khz input jitter tolerance characteristics sym min max units conditions/notes? 1 jitter tolerance for 1hz input 0 .80 uipp 1,3,6-11, 18-19,21-23,25 2 jitter tolerance for 5hz input 0 .70 uipp 1,3,6-11, 18-19,21-23,25 3 jitter tolerance for 20hz input 0.60 uipp 1,3,6-11,18-19,21-23,25 4 jitter tolerance for 300hz inpu t 0.20 uipp 1,3,6-1 1,18-19,21-23,25 5 jitter tolerance for 400hz inpu t 0.15 uipp 1,3,6-1 1,18-19,21-23,25 6 jitter tolerance for 700hz inpu t 0.08 uipp 1,3,6-1 1,18-19,21-23,25 7 jitter tolerance for 2400hz inpu t 0.02 uipp 1,3,6-1 1,18-19,21-23,25 8 jitter tolerance for 3600hz inpu t 0.01 uipp 1,3,6-1 1,18-19,21-23,25
MT9041b data sheet 20 zarlink semiconductor inc. ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - 1.544mhz input jitter tolerance characteristics sym min max units conditions/notes? 1 jitter tolerance for 1hz input 150 uipp 1,4,6-11,18-19,21-23,26 2 jitter tolerance for 5hz input 140 uipp 1,4,6-11,18-19,21-23,26 3 jitter tolerance for 20hz input 130 uipp 1,4,6-11,18-19,21-23,26 4 jitter tolerance for 300hz input 35 uipp 1,4,6-11,18-19,21-23,26 5 jitter tolerance for 400hz input 25 uipp 1,4,6-11,18-19,21-23,26 6 jitter tolerance for 700hz input 15 uipp 1,4,6-11,18-19,21-23,26 7 jitter tolerance for 2400hz input 4 uipp 1,4,6-11,18-19,21-23,26 8 jitter tolerance for 10khz input 1 uipp 1,4,6-11,18-19,21-23,26 9 jitter tolerance for 100khz input 0.5 uipp 1,4,6-11,18-19,21-23,26 ac electrical characteristics - 2.048mhz input jitter tolerance characteristics sym min max units conditions/notes? 1 jitter tolerance for 1hz input 150 uipp 1,5,6-11,18-19,21-23,27 2 jitter tolerance for 5hz input 140 uipp 1,5,6-11,18-19,21-23,27 3 jitter tolerance for 20hz input 130 uipp 1,5,6-11,18-19,21-23,27 4 jitter tolerance for 300hz inpu t 50 uipp 1,5,6-11,18-19,21-23,27 5 jitter tolerance for 400hz inpu t 40 uipp 1,5,6-11,18-19,21-23,27 6 jitter tolerance for 700hz inpu t 20 uipp 1,5,6-11,18-19,21-23,27 7 jitter tolerance for 2400hz in put 5 uipp 1,5,6-11,18-19,21-23,27 8 jitter tolerance for 10khz input 1 uipp 1,5,6-11,18-19,21-23,27 9 jitter tolerance for 100khz i nput 1 uipp 1,5,6-11,18-19,21-23,27 ac electrical characteristics - osci 20mhz master clock input characteristics sym min typ max units conditions/notes? 1 frequency accuracy (20 mhz nominal) -0 0 +0 ppm 15,18 2 -32 0 +32 ppm 16,19 3 -100 0 +100 ppm 17,20 4 duty cycle 40 50 60 % 5 rise time 10 ns 6 fall time 10 ns
MT9041b data sheet 21 zarlink semiconductor inc. ? notes: voltages are with respect to ground (v ss ) unless otherwise stated. supply voltage and operating temperature are as per recommended operating conditions. timing parameters are as per ac electrical characteristics - timing parameter measurement voltage levels 1. normal mode selected. 2. freerun mode selected. 3. 8khz frequency mode selected. 4. 1.544mhz frequency mode selected. 5. 2.048mhz frequency mode selected. 6. master clock input osci at 20mhz 0ppm. 7. master clock input osci at 20mhz 32ppm. 8. master clock input osci at 20mhz 100ppm. 9. selected reference input at 0ppm. 10. selected reference input at 32ppm. 11. selected reference input at 100ppm. 12. for freerun mode of 0ppm. 13. for freerun mode of 32ppm. 14. for freerun mode of 100ppm. 15. for capture range of 230ppm. 16. for capture range of 198ppm. 17. for capture range of 130ppm. 18. 25pf capacitive load. 19. osci master clock jitter is less than 2nspp, or 0.04uipp where1uipp=1/20mhz. 20. jitter on reference i nput is less than 7nspp. 21. applied jitter is sinusoidal. 22. minimum applied input jitter magnitude to regain synchronization. 23. loss of synchronization is obtained at slightly higher input jitter amplitudes. 24. within 10ms of the state, reference or input change. 25. 1uipp = 125us for 8khz signals. 26. 1uipp = 648ns for 1.544mhz signals. 27. 1uipp = 488ns for 2.048mhz signals. 28. 1uipp = 323ns for 3.088mhz signals. 29. 1uipp = 244ns for 4.096mhz signals. 30. 1uipp = 122ns for 8.192mhz signals. 31. 1uipp = 61ns for 16.384mhz signals. 32. no filter. 33. 40hz to 100khz bandpass filter. 34. with respect to reference input signal frequency. 35. after a rst or trst . 36. master clock duty cycle 40% to 60%.

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